For memory and storage devices whose memory cells can endure a limited number of write cycles, some cells might fail much earlier than the others due to uneven write traffic to cells by system applications. In this case, a device becomes unusable much sooner than the expected device lifetime, as expected device lifetimes are determined based on relatively even write usage of the cells. Examples of non-volatile memory devices with limited write endurance include flash memory, phase-change memory (PCM) and magneto-resistive random-access memory (MRAM).
Wear leveling is the approach of (relatively) evenly distributing writes across all device cells, thus extending the device lifetime. Typically it is achieved through dynamically re-mapping a physical address (i.e., the physical device addresses that would be used in the absence of wear leveling) to a different actual device address.
Wear leveling is particularly important and challenging for memory devices that operate as the memory of a computer system. Because the memory is relatively closer to the processor, ideal wear leveling processes are robust and efficient to handle high write traffic. They also have low performance cost and minimal write overhead. In addition, it is important for wear leveling processes to be highly secure against malicious attacks that compromise the security of the host system.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.